Method of manufacturing semiconductor device, mask and semiconductor device

ABSTRACT

A method of manufacturing a semiconductor device answerable to refinement of circuits by correctly connecting adjacent small patterns with each other with excellent reproducibility in connective exposure and a semiconductor device manufactured by this method are proposed. According to this method of manufacturing a semiconductor device, connective exposure is performed by dividing a pattern formed on a semiconductor substrate into a plurality of patterns and exposing the plurality of divided patterns in a connective manner, by forming marks for adjusting arrangement of the patterns to be connected with each other on the semiconductor substrate before exposing patterns of a semiconductor element and connectively exposing the patterns of the semiconductor element in coincidence with the marks for adjusting arrangement.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of manufacturing asemiconductor device by performing connective exposure. The presentinvention also relates to a mask employed in the method of manufacturinga semiconductor device and a semiconductor device manufactured by thismethod.

2. Description of the Background Art

Connective exposure is performed in order to manufacture a semiconductordevice such as an image sensor having an element size (device size, chipsize) larger than the exposable size of an exposer. According to thisconnective exposure, a large-pattern semiconductor device ismanufactured by temporarily dividing a large pattern to be transferredinto a plurality of exposable small patterns and exposing the pluralityof divided small patterns in a connective manner. A semiconductor devicehaving a plurality of layers can be manufactured by repeating steps offorming single layers by connective exposure.

As a technique of such connective exposure, U.S. Pat. No. 6,194,105, forexample, describes a method of dividing a mask into a plurality of maskthrough a blind while forming opaque trace patterns on the respectivemasks. A necessary mask is selected from the plurality of divided masksand arranged on a prescribed position for performing exposure.Arrangement of the masks is so adjusted as to align the trace patternsformed on the masks with each other. A large-sized pattern is formed byrepeating such movement of the masks and exposure. As to dicing regions,dicing lines are first formed on a wafer for forming patterns to beconnected with each other along the dicing lines so that overlapquantities of the patterns can be easily controlled and the patterns canbe arranged to have a constant width along the dicing lines by settingthe overlap quantities, as described in U.S. Pat. No. 6,225,013.

Japanese Patent Laying-Open No. 02-005568 (1990) describes a waferstepper type photolithographic manufacturing method forming an array ofpatterns on a wafer, moving the wafer for performing exposure andrepeating such operations until the wafer is entirely covered with thearray of patterns. According to this method, alignment marks are exposedon a substrate through photolithography, and alignment patterns areformed in correspondence to the alignment marks. Then, an array of otheralignment patterns is formed by alignment through the alignment marks.The aforementioned gazette describes that a large image region can beformed through a conventional wafer stepper according to this method.According to this method utilizing offset printing throughphotolithography, however, adjacent patterns are not superposed witheach other and hence misalignment in printing disadvantageously resultsin disconnection on junctions between the adjacent patterns.

SUMMARY OF THE INVENTION

Connective exposure is performed by repeating operations of forming apattern on a substrate by exposure through a mask, thereafter exchangingthe mask, moving a stage of an exposer, performing exposure andconnecting a new pattern to the previously formed pattern. In suchconnective exposure, therefore, it is important to correctly connectadjacent patterns with each other with excellent reproducibility, andpattern connection accuracy depends on accuracy for setting the mask onthe exposer, stage accuracy of the exposer etc. Under the presentcircumstances, the patterns are superposed with each other with marginsso that circuits are not disconnected on the connected portions of thepatterns upon occurrence of an error in connection, leading to ahindrance to refinement etc. of the circuits.

An object of the present invention is to provide a method ofmanufacturing a semiconductor device answerable to refinement ofcircuits by correctly connecting adjacent small patterns with each otherwith excellent reproducibility in connective exposure and asemiconductor device manufactured by this method. Another object of thepresent invention is to provide a mask useful in such manufacture.

The present invention provides a method of manufacturing a semiconductordevice through connective exposure performed by dividing a patternformed on a semiconductor substrate into a plurality of patterns andexposing the plurality of divided patterns in a connective manner, byforming marks for adjusting arrangement of the patterns to be connectedwith each other on the semiconductor substrate before exposing patternsof a semiconductor element and connectively exposing the patterns of thesemiconductor element in coincidence with the marks for adjustingarrangement.

According to another aspect, the present invention also provides a maskemployed in manufacture of a semiconductor device through connectiveexposure for forming marks for adjusting arrangement of patterns to beconnected with each other on a substrate before exposing patterns of asemiconductor element, in which the marks for adjusting arrangement areformed on either an X-dicing region or a Y-dicing region of thesubstrate. According to still another aspect, the present inventionfurther provides a mask employed for exposing patterns of asemiconductor element to be connected with each other, in which marksfor adjusting arrangement of the patterns to be connected with eachother are formed on either an X-dicing region or a Y-dicing region of asubstrate.

The present invention further provides a semiconductor device having asemiconductor element larger in size than an exposable region of anexposer, in which a mark formed on a substrate for adjusting arrangementof an exposed pattern is arranged on either an X-dicing region or aY-dicing region.

According to the present invention, patterns can be correctly connectedwith each other in connective exposure, and circuits can be refined byreducing the quantities of superposition of the patterns. Further,correct connective exposure can be performed with excellentreproducibility in manufacture of an image sensor, an infrared sensor, alarge-sized liquid crystal display or the like having a size larger thanthat of an exposable region of an exposer. The present invention is notrestricted to such devices, but is also applicable to a memory, a massstorage device and a logic device.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a semiconductor device having a size largerthan that of an exposable region of an exposer;

FIGS. 2A to 2D are process drawings showing a method of manufacturing aMOS device according to the present invention;

FIG. 3 is a flow chart as to formation of arrangement adjusting marksand element isolation regions in the method of manufacturing a MOSdevice according to the present invention;

FIG. 4 is a plan view of a mask employed for forming arrangementadjusting marks in Example 1 of the present invention;

FIG. 5 is a plan view showing arrangement of masks employed for formingthe arrangement adjusting marks in Example 1 of the present invention;

FIG. 6 is a plan view of a mask employed for forming an element patternin Example 1 of the present invention;.

FIG. 7 is an alignment tree in Example 2 of the present invention;

FIGS. 8A and 8B are plan views showing a mask and a semiconductor waferemployed and manufactured in Example 3 of the present inventionrespectively;

FIGS. 9A and 9B are plan views showing a mask and a semiconductor waferemployed and manufactured in Example 4 of the present inventionrespectively; and

FIG. 10 is a plan view of a MOS device manufactured according to thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a plan view of a semiconductor device 1 manufactured byconnecting three masks with each other. This semiconductor device 1comprises an element region 2 provided on the center, circuit regions 3provided on both ends and a dicing region 4 provided on the outer edge.When the size of semiconductor device 1 is large than that of anexposable region of an exposer, a pattern formed on a semiconductorsubstrate is divided into a plurality of patterns 5 a, 5 b and 5 c incoincidence with the size of the exposable region so that the pluralityof divided patterns 5 a, 5 b and 5 c are exposed in a connective mannerfor manufacturing semiconductor device 1 of a large size. The presentinvention provides a method of manufacturing a semiconductor devicethrough connective exposure by forming marks (alignment marks and/orsuperposition inspection marks, for example, hereinafter referred to as“arrangement adjusting marks”) for adjusting arrangement of patterns tobe connected with each other on a substrate before exposing patterns ofa semiconductor element and connectively exposing the patterns of thesemiconductor element in coincidence with the marks for adjustingarrangement. The marks for adjusting arrangement are previously formedon the substrate before connectively exposing the patterns of thesemiconductor element for performing connective exposure in coincidencewith these marks, so that patterns of the semiconductor elementsubsequent to a first layer can be aligned with each other withreference to the marks for adjusting arrangement, for example.Therefore, the patterns can be so correctly connected with each otherthat circuits can be refined by reducing the quantities of superpositionof the patterns. Further, superposed states of the marks for adjustingarrangement are so measured that the exposer can be previously adjustedon the basis of the measured values.

As a specific mode of the present invention, such a mode that thesemiconductor substrate has a first region and a second region adjacentto each other so that marks for adjusting arrangement of thesemiconductor element patterns to be connected with each other areformed on the first region and the second region through a first mask, asemiconductor element pattern is thereafter formed by exposing the firstregion in coincidence with the arrangement adjusting marks through asecond mask, another semiconductor element pattern is formed by exposingthe second region in coincidence with the arrangement adjusting marksthrough a third mark and a first connective element pattern is formed byconnecting the element pattern of the first region and the elementpattern of the second region with each other is preferable, for example.

Further, such a mode that the method has the steps of forming stillanother semiconductor element pattern by exposing the first regionthrough a fourth mask after forming the first connective elementpattern, forming a further semiconductor element pattern by exposing thesecond region through a fifth mask and forming a second connectiveelement pattern by connecting the element patterns of the first regionand the element patterns of the second region with each other whileadjusting arrangement of the fourth mask through the element patternformed through the second mask in the first region and adjustingarrangement of the fifth mask through the element pattern formed throughthe third mask in the second region is preferable in a point thatpositional accuracy of the first connective element pattern and thesecond connective element pattern is improved.

A mode of forming the marks for adjusting arrangement by exposurethrough a single mask is preferable. In conventional connectiveexposure, the pattern of a first layer is formed through a plurality ofmasks and hence array precision of the pattern and marks is deterioratedthrough set accuracy of the plurality of masks and slide accuracy of astage. According to the present invention, on the other hand, the marksfor adjusting arrangement are so formed through the single mask thatarray precision is not deteriorated through set accuracy of theunexchanged mask.

A mode of forming the marks for adjusting arrangement by locallyexposing a region of a mask to be formed with the marks for adjustingarrangement is preferable. The marks can be formed with stage accuracyof an exposer by repeating operations of locally exposing the portion ofthe marks for adjusting arrangement, thereafter moving a stage of theexposer and similarly locally exposing an adjacent region. Further,distortion can be reduced for further improving exposure accuracy byexposing a mark forming region of the mask.

According to this method, a mode of arranging arrangement adjustingmarks 86 in an array grid 88 for arranging product chips in asemiconductor wafer 87 can be employed as shown in FIG. 8B, for example.Alternatively, a mode of arranging arrangement adjusting marks 96 onregions out of an array grid 98 in a semiconductor wafer 97 can beemployed, as shown in FIG. 9B. According to this mode, the marks can bearrayed through the same mask with slide accuracy of a stage, so thatadjacent patterns can be superposed with each other within the range ofalignment accuracy and distortion in subsequent steps. Further, highexposure accuracy can be attained by performing exposure while centeringthe arrangement adjusting marks, while a dicing region can be narrowed,the throughput can be improved and productivity for element chips can beimproved particularly according to the latter mode arranging thearrangement adjusting marks on the regions out of the array grid.

A mode of adjusting the positional relation between adjacent marks ispreferable in the step of forming the marks for adjusting arrangement.Positional accuracy of marks for adjusting arrangement in a subsequentprocessing lot can be improved by forming superposition inspection marksfor measuring positional relation between adjacent marks on the marksfor adjusting arrangement, measuring the positional accuracy through theinspection marks, feeding back measured data to the exposer andadjusting the exposer. Further, superposition accuracy of elementpatterns of second and subsequent layers can be improved by adjustingarrangement with reference to highly accurate marks. As to superpositionof element patterns, therefore, a design allowance can be more reducedas compared with the prior art, for allowing refinement of circuits.

A mode of forming the marks for adjusting arrangement on thesemiconductor substrate, performing connective exposure of the patternof the semiconductor element in coincidence with the marks for adjustingarrangement and thereafter further performing connective exposure incoincidence with the connected pattern is possible. This mode ispreferable in a case where positional accuracy of a formed pattern andanother pattern further formed on this position is regarded asimportant. A general manufacturing method and a general design method ina case of performing no connective exposure in a superpositioninspection apparatus or an APC (advanced process control) system forcorrecting a superposition error can be applied. According to theinventive manufacturing method, positional accuracy of the marks foradjusting arrangement formed on the substrate is so high that sufficientpositional accuracy can be obtained through simple arrangement on apreviously formed pattern.

A mode of forming the marks for adjusting arrangement on either anX-dicing region or a Y-dicing region of the semiconductor substrate ispreferable. In general, alignment marks in X- and Y-directions areformed on X- and Y-dicing regions respectively, in order to adjustpositions in the X- and Y-directions. If the alignment marks in the X-and Y-directions are similarly formed on the X- and Y-dicing regionsrespectively also in connective exposure, however, the marks foradjusting arrangement are disadvantageously formed on a pattern regionof the semiconductor element connected in a subsequent step. Therefore,the marks for adjusting arrangement are preferably formed on either theX-dicing region or the Y-dicing region of the substrate. In each of themask employed for forming the marks for adjusting arrangement and a maskemployed for forming the semiconductor element patterns to be connectedwith each other, therefore, the marks for adjusting arrangement arepreferably formed on either the X-dicing region or the Y-dicing regionof the substrate. A semiconductor device having a semiconductor elementlarger in size than an exposable region of an exposer and marks foradjusting arrangement formed on either an X-dicing region or a Y-dicingregion of a substrate can be manufactured through such masks.

Example 1

According to Example 1, a MOS (metal oxide semiconductor) device wasmanufactured through connective exposure. FIG. 10 is a plan view showingthe manufactured MOS device 10. FIG. 10 omits illustration of aninterlayer dielectric film and wires, in order to clearly illustrate thestructure of MOS device 10. This MOS device 10 has a connected portionA-A, and is constituted of photodiodes 10 a, gate electrodes 15,impurity regions 16 such as source and drain regions, element isolationregions 14, contacts 18 etc. FIG. 2D is a sectional view taken along theline IID-IID in FIG. 10. As shown in FIG. 2D, a MOS device 20 compriseselement isolation regions 24 on a substrate 21, and has gate electrodes25 and impurity regions 26. An interlayer dielectric film 27 is formedon substrate 21, and contacts 28 are formed between substrate 21 andwires 29 formed on interlayer dielectric film 27.

FIGS. 2A to 2D show a method of manufacturing MOS device 20. Referringto each of FIGS. 2A to 2D, symbol A-A denotes a connected portion, andreference numerals (2-1) and (2-2) show a step of manufacturing marksfor adjusting arrangement and a step of manufacturing a semiconductorelement region respectively. First, a resist film 22 was formed onp-type semiconductor substrate 21 and patterned by exposure anddevelopment through a mask, in order to form arrangement adjusting marks23 (FIG. 2A). Then, arrangement adjusting marks 23 were formed byetching (FIG. 2B), an SiO₂ film was formed by oxidation, and an Si₃N₄film was formed on the SiO₂ film by LPCVD. Then, another resist film wasformed and element isolation regions were connectively exposed,developed and patterned while adjusting arrangement of masks througharrangement adjusting marks 23. Thereafter the Si₃N₄ film wasselectively removed by etching, and element isolation regions 24 of SiO₂were formed through field oxidation by heat treatment at a temperatureof 1000° C. for 150 minutes (FIG. 2C). Then, the Si₃N₄ film wasseparated, and MOS device 20 was manufactured by depositing polysilicon,forming gate electrodes 25, thereafter forming impurity regions 26 andfurther forming interlayer dielectric film 27, contacts 28 and wires 29(FIG. 2D).

FIG. 3 is a flow chart as to formation of the arrangement adjustingmarks and the element isolation regions. The arrangement adjusting markswere formed on the substrate before exposing patterns of the isolationregions in a semiconductor element, as shown in FIG. 3. First, resistwas applied onto the substrate (step 1) (steps 2 to 12 are hereinafterreferred to as S2 to S12), exposed (S2) and thereafter developed (S3).Then, pattern superposition accuracy was measured (S4), and thesubstrate was etched when the accuracy was within a prescribed standard(S5). The measured value was fed back for adjusting the exposer forcorrectly superposing portions to be connected with each other in asubsequent processing lot (S4). If the measured value of thesuperposition accuracy is out of the prescribed standard, the resist isremoved and another resist is applied for feeding back theaforementioned measured value and performing exposure.

The exposure (S2) was performed through a single mask 40 shown in FIG.4, and connective exposure was performed by moving a stage of theexposer and arranging the substrate. According to Example 1, thearrangement adjusting marks were formed through this single pattern mask40. Therefore, mask 40 was not exchanged and it was possible to suppressaccuracy deterioration resulting from set accuracy of mask 40. Mask 40comprised a pattern region 49 for forming a pattern of a semiconductorelement and X-dicing regions 45 and 46 with superposition inspectionpatterns 41 to 44, an X-directional alignment pattern 47 and aY-directional alignment pattern 48 provided on X-dicing regions 45 and46. The arrangement adjusting marks were formed only on X-dicing regions45 and 46 through this mask 40. Therefore, no marks for adjustingarrangement were formed on a pattern region for a semiconductor elementconnected in a subsequent step.

FIG. 5 is a plan view showing arrangement of masks employed for formingthe arrangement adjusting marks. According to Example 1, single maskswere employed and connective exposure was performed by moving the stageof the exposer to superpose adjacent masks with each other, as shown inFIG. 5. Adjacent patterns were so arranged that a superpositioninspection pattern 51 a for a pattern 50 a coincided with asuperposition inspection pattern 51 b for a leftwardly adjacent pattern50 b, for example, as shown in FIG. 5. Superposition inspection pattern51 a was rendered larger than superposition inspection pattern 51 b.Superposition accuracy was measured by measuring misalignment of innersuperposition inspection pattern 51 b with respect to outersuperposition inspection pattern 51 a. Similarly, another superpositioninspection pattern 52 a for pattern 50 a was arranged to coincide withanother superposition inspection pattern 52 b for leftwardly adjacentpattern 50 b, for similarly measuring misalignment. In addition, stillanother superposition inspection pattern 53 a for pattern 50 a wasarranged to coincide with a superposition inspection pattern 53 c for apattern 50 c adjacent on the other side while a superposition inspectionpattern 54 a was arranged to coincide with a superposition inspectionpattern 54 c, for similarly measuring misalignment. Misalignment of theremaining patterns was also measured. According to Example 1, theresults of measurement were fed back to the exposer and adjusted afterthe measurement of superposition accuracy, whereby positional accuracyof the arrangement adjusting marks was improved also as to subsequentlots so that arrangement accuracy of element patterns arranged withreference to the arrangement adjusting marks was continuously improvedand maintained also between different lots.

The element isolation regions were formed after forming the arrangementadjusting marks. First, as shown in FIG. 3, an oxide film and a nitridefilm were formed on the substrate (S6), thereafter resist was applied(S7), and the patterns of the element isolation regions were exposed asthe patterns of the semiconductor element (S8). After the exposure,development was performed (S9), superposition was inspected (S10), thenitride film was etched (S11) and field oxidation was performed (S12)for forming the element isolation regions, as shown in FIG. 3. Thesemiconductor element patterns were exposed (S8) by moving the stage incoincidence with a first alignment mark formed on the substrate as thearrangement adjusting mark, exposing the mark through a mask 1 (S8-1),moving the stage in coincidence with a next alignment mark and exposingthe mark through a mask 2 (S8-2) and repeating such operations up to amask m thereby performing connective exposure (S8-3). Superposition wasinspected (S10) between an inspection pattern formed through mask 1 andan inspection pattern on the substrate (S10-1) and inspected between aninspection pattern formed through mask 2 and the inspection pattern onthe substrate (S10-2), while such operations were repeated up to themask m.

The patterns of the semiconductor element were exposed (S8) through apattern mask 60 shown in FIG. 6, and the substrate was arranged byadjusting the position of the stage of the exposer for performingconnective exposure. Mask 60 comprised a semiconductor element patternregion 69 and X-dicing regions 65 and 66 with superposition inspectionpatterns 61 to 64, an X-directional alignment pattern 67 and aY-directional alignment pattern 68 provided on X-dicing regions 65 and66. Arrangement adjusting marks were formed only on the X-dicing regions65 and 66 through this mask 60. Therefore, no arrangement adjustingmarks were formed on a circuit region of a pattern connected in asubsequent step. In a semiconductor device as obtained, the size of thesemiconductor element was larger than that of an exposable region of theexposer, and the arrangement adjusting marks were arranged only on theX-dicing regions.

Example 2

According to Example 2, a MOS device was manufactured similarly toExample 1 except that gate electrodes were formed by further performingconnective exposure in coincidence with the patterns of elementisolation regions formed by connective exposure after the connectiveexposure of the element isolation regions. FIG. 7 is an alignment treeof Example 2. As shown in FIG. 7, marks for adjusting arrangement ofrespective patterns of the element isolation regions were formed on asubstrate, for forming element isolation regions 1 to 3 by performingconnective exposure in coincidence with the marks for adjustingarrangement. Then, gate electrodes 1 to 3 were formed by connectiveexposure through alignment with the patterns of element isolationregions 1 to 3, for manufacturing the MOS device.

In the manufactured MOS device, positional accuracy of gate electrodes 1to 3 with respect to element isolation regions 1 to 3 was so high that ahigh-characteristic MOS device was obtained since superposition accuracybetween patterns of element isolation regions and patterns of gateelectrodes is regarded as important in a MOS device. Further, positionalaccuracy of the arrangement adjusting marks formed on the substrate wasso high that sufficient positional accuracy was attained by simplyadjusting arrangement with respect to previously formed patterns withoutadjusting the arrangement between right and left patterns. Therefore, itwas possible to reduce the processing time for superposition inspection.Further, a general manufacturing method and a general design method in acase of performing no connective exposure in a superposition inspectionapparatus or an APC (advanced process control) system for correcting asuperposition error, applied to the gate electrodes in Example 2, canalso be applied to wire patterns or hole patterns of a higher layer asshown in FIG. 7. In particular, it was possible to accurately connectwires 29 on the connected portion as shown in FIG. 2D.

Example 3

When forming arrangement adjusting marks on a substrate according toExample 3, a region 85 of arrangement adjusting marks including asuperposition inspection mark 82, an X-directional alignment mark 83 anda Y-directional alignment mark 84 was locally exposed in a mask 81 asshown in FIG. 8A. In this exposure, mask 81 was set on an exposer tocenter region 85. After the exposure, a wafer stage of the exposer wasmoved so that exposure and movement of the stage were repeated forthereafter performing development and etching. Consequently, as shown inFIG. 8B, a semiconductor wafer 87 having arrangement adjusting marks 86arranged in an array grid 88 for arraying product chips was obtained formanufacturing the MOS device similarly to Example 1.

According to Example 3, the same mask was employed for forming thearrangement adjusting marks by sliding the wafer stage, whereby it waspossible to perform patterning within the range of slide accuracy withno error resulting from mask arrangement as compared with a mode ofemploying a plurality of masks and arranging the masks every exposure.Consequently, it was possible to superpose adjacent patterns within therange of alignment accuracy and distortion in subsequent steps.According to the mode of Example 3, it was possible to set and exposethe mask to center the region for forming the arrangement adjustingmarks, whereby distortion was reduced as compared with a case whereregions for forming arrangement adjusting marks were provided around anexposed region and it was possible to further improve exposure accuracy.

Example 4

When forming marks for adjusting arrangement on a substrate according toExample 4, a region 95 for forming arrangement adjusting marks includingan X-directional alignment mark 93 and a Y-directional alignment mark 94in a mask 91 was locally exposed as shown in FIG. 9A. In this exposure,mask 91 was set on an exposer to center region 95 on an exposure region.After the exposure, a wafer stage of the exposer was moved so thatexposure and movement of the stage were repeated for thereafterperforming development and etching. Consequently, as shown in FIG. 9B, asemiconductor wafer 97 having arrangement adjusting marks 96 arranged onregions out of an array grid 98 for arraying product chips was obtainedfor manufacturing the MOS device similarly to Example 1.

According to Example 4, the same mask was employed for forming thearrangement adjusting marks by sliding the wafer stage, whereby it waspossible to perform patterning within the range of slide accuracysimilarly to Example 3. Consequently, it was possible to superposeadjacent patterns with each other within the range of alignmentaccuracy, distortion and array accuracy in subsequent steps. Further, itwas possible to set and expose the mask to center the region for formingthe arrangement adjusting marks on the exposure region, wherebydistortion was reduced as compared with a case where arrangementadjusting marks were provided around an exposed region and it waspossible to further improve exposure accuracy. In addition, arrangementadjusting marks 96 were arranged on the regions out of array grid 98 forarraying the product chips, whereby it was possible to reduce the sizeof dicing regions, improve the throughput and increase manufacturingefficiency for the semiconductor device.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

1-12. (canceled)
 13. A semiconductor device being larger in size thanthe size of an exposable region of an exposer, wherein marks includingat least one mark different in size from the other marks, for adjustingarrangement of patterns to be connected with each other on a substratebefore exposing patterns of a semiconductor element, wherein said marksfor adjusting arrangement through aliment said one mark and other markare formed on a substrate for adjusting arrangement of an exposedpattern is arranged.
 14. The semiconductor device according to claim 13,forming said marks for adjusting arrangement on either an X-dicingregion or a Y-dicing region of said semiconductor substrate.
 15. Thesemiconductor device according to claim 13, arranging said marks foradjusting arrangement in an array grid for arraying product chips in asemiconductor wafer.
 16. The semiconductor device according to claim 13,arranging said marks for adjusting arrangement on a region out of anarray grid in a semiconductor wafer.